Semiconductor device fabrication is the process used to create “chips”, i.e., integrated circuits, which are present in everyday electrical and electronic devices. Integrated circuit fabrication is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a semiconductor wafer. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors. The entire manufacturing process from start to packaged chips ready for shipment often takes at least six to eight weeks and is performed in highly specialized facilities referred to as fabs, which often cost several billions of dollars to build.
FIG. 1 shows a typical wafer 100 on which integrated circuits can be manufactured. The wafer includes a grid-like pattern of dies 102. After the wafer 100 is processed in its entirety, it is diced up so each die 102 corresponds to a single integrated circuit. Thus, one wafer often yields tens, hundreds, or even thousands of integrated circuits, depending on the size and complexity of the integrated circuits and the size of the wafer.
At various points in the manufacturing process, the dies 102 are subjected to a variety of electrical tests to determine if they function properly. The electrical tests are performed with an electronic tester that presses tiny probes against the wafer's surface. Dies 102 are often designed with “testability features” such as “built-in self-test” to speed testing, and reduce test costs.
Some of these electrical tests may be as simple as whether a die 102 is “good” or “faulty”, wherein the good dies are packaged and sold to customers and faulty chips are disposed of. Other electrical tests may characterize a die 102 in more detailed fashion, assigning the die to one of several different levels of functionality. For example, if a microprocessor chip is designed to operate effectively with a clock frequency of 1.1 GHz, but when manufactured only in fact operates effectively with a clock frequency of 564 MHz, the chip could still be useful in some contexts even though it will not process data as fast as hoped. Therefore, dies with less than optimal functionality can be “binned” out and later sold to customers at a reduced price, thereby allowing the manufacturer to still realize some revenue from the imperfect integrated circuits.
In any event, the dies are tested and categorized according to their level of functionality. For example, in FIG. 1, dies 102A could be categorized as “good”, while dies 102B could be categorized as “faulty”. Other dies could be categorized to these or other functionality levels. Unfortunately, due to the large number of process steps and significant time needed to manufacture the integrated circuits, it is extremely difficult to adequately diagnose what causes a particular die to exhibit lower functionality relative to another die. Often the location of the lower functional dies on the wafer will exhibit a pattern or signature that can be used to help determine the cause of the reduced functionality. Since many of the process steps used do not physically align the wafers before processing, these fault patterns or signatures often do not appear in the same area, wafer to wafer. This makes diagnostic procedures more difficult. Consequently, there is an on-going need for improved methods and systems for diagnosing problems that give rise to different levels of functionality in processed wafers. These diagnostic methods and systems allow manufacturing problems to be fixed, which improves yields and leads to increased revenues for the manufacturer.